This Startup Reckons Its Chiplet Interconnect Tech Can Best Intel, TSMC

Silicon Valley startup Eliyan thinks its technology for enabling chiplet-based designs can best those from semiconductor giants Intel and TSMC by providing better performance, higher efficiency, fewer manufacturing issues, and more supply chain options.

The upstart announced on Tuesday that it has raised $40 million from investors – including the venture arms of Intel and Micron – to help commercialize its NuLink interconnect tech, which it is positioning as an alternative to advanced packaging solutions like TSMC's chip-on-wafer-on-substrate (CoWoS) and Intel's embedded multi-die interconnect bridge (EMIB).

Advanced packaging technologies are becoming increasingly critical to the semiconductor industry because a growing number of chip designers are moving to system-on-package designs – comprising multiple chiplets for improved performance, efficiency, and costs benefits over traditional monolithic dies.

Most famously, AMD has been able to win CPU market share against Intel over the last few years because it turned to a chiplet-based architecture for its Ryzen and Epyc processors. Now Intel, among other companies, is hoping chiplets will help it strike back with more powerful chips in the coming years.

Eliyan's founders, which include some industry veterans, hope they can win business from this growing group of chiplet adherents by helping them overcome existing hurdles associated with advanced packaging tech used to connect chiplets on packages.

In fact, Ramin Farjadrad, Eliyan's CEO, tells The Register that Intel's investment represents a larger interest from the x86 goliath in exploring the startup's tech. That wouldn't be a complete surprise, given that many companies Intel invests in end up working with the chipmaker in one way or another.

"Part of Intel's philosophy in investing in Eliyan was finding an alternative to EMIB. And Intel is very seriously working with us," he says.

Patrick Soheili, another Eliyan co-founder, was careful to add that the startup views its NuLink interconnect "as a complement" and not a "replacement" to EMIB and Intel's other advanced packaging technology, known as Foveros.

But even though Eliyan wants – and likely needs – to play nice with Intel because the semiconductor giant could represent substantial business in the future, Eliyan is still keen to point out how its NuLink interconnect is better than advanced packaging solutions currently available.

Farjadrad says that TSMC's CoWoS and Intel's EMIB have their benefits – mainly in the high bandwidth and low power at which chiplets can communicate on the same package. EMIB can also enable the creation of large and complex system-on-package designs, like Intel's upcoming Sapphire Rapids chips.

However, there are notable drawbacks, according to Farjadrad. These include high costs, low manufacturing yields, long development cycles, and a limited supply chain.

Farjadrad, who was previously an executive at Marvell Semiconductor, claimed that those downsides don't exist with Eliyan's NuLink tech.

"We effectively remove all the negative challenges and drawbacks of advanced packaging," he says.

NuLink can also enable larger and more complex system-on-package designs to improve performance and efficiency, according to Farjadrad. For example, he says, NuLink can let a chip designer place a larger number of high-bandwidth memory chiplets on a processor compared to other approaches. This, in turn, can provide a significant boost to applications that use large datasets.

Farjadrad claims NuLink can accomplish these feats by connecting chiplets through high-density wires that travel within the organic substrate, which serves as the foundation of the system-on-package. This is in contrast to CoWoS, which uses a connective layer between the chiplets and substrate called the silicon interposer, and to EMIB, which connects chiplets via silicon bridges embedded within the substrate.

"This die-to-die solution that we developed is a very efficient way to push an order of magnitude more bandwidth within each wire at no power compromise," he says.

NuLink didn't come out of nowhere

Farjadrad says the interconnect tech is considered a superset of bunch-of-wires (BoW) – another die-to-die interface he developed while running a previous startup, Aquantia. BoW is now the chiplet interconnect scheme used by the Open Compute Project – the organization founded by Meta that steers open source datacenter and chip designs for the world's largest consumers of servers.

One important benefit of Eliyan's approach is that NuLink can be implemented by most contract chip manufacturers, according to Farjadrad. He name-checked USA's GlobalFoundries, South Korea's Samsung, and Taiwan's UMC as examples and reckons this could help with geopolitical situations where a country loses access to a chipmaker with advanced packaging capabilities.

• AMD was right about chiplets, Intel's Gelsinger all but says
• TSMC wants to unleash a flood of chiplet designs with 3DFabric Alliance
• Who's been copying AMD's homework? Intel lifts the lid on its hip chip packaging to break up chips into chiplets
• Thanks to 'resilient' American cloud plus games consoles, AMD squeezes into winter

For instance, if China were to invade Taiwan and take over TSMC's factories, chipmakers elsewhere could manufacture chiplet-based designs using NuLink, according to Farjadrad.

But this depends on whether Eliyan's tech remains accessible to the wider industry in the long run. That could change, if a chipmaker decides to acquire the startup.

"The technology is differentiating enough that you can then also imagine that maybe there's an offensive or defensive strategy by one of the large guys to want to keep it for themselves," Soheili says.

On the other hand, NuLink is compliant with the Universal Chiplet Interconnect Express (UCIe) standard developed by Intel, which could help with the startup's long-term viability as an standalone company, according to Soheili.

"That would encourage us to stay independent and leverage that," he says. ®