Intel, AMD Team With Tech Titans For X86 ISA Overhaul

The shape of the x86 instruction set architecture (ISA) is evolving. On Tuesday, Intel and AMD announced the formation of an ecosystem advisory group intended to drive greater consistency between the brands' x86 implementations.

Intel and AMD have been co-developing the x86-64 instruction for decades. But while end user workloads have enjoyed cross-compatibility between the two chipmakers' products, this has been far from universal.

"x86 is the de facto standard. It's a strong ecosystem, but it's one that really Intel and AMD have co-developed in a way, but an arm's length, and you know, that has caused some inefficiencies and some drift in portions of the ISA over time." AMD EVP of datacenter solutions Forrest Norrod said during a press briefing ahead of the announcement.

The introduction of advanced vector extensions (AVX) is the most obvious example of where compatibility across Intel and AMD platforms hasn't always been guaranteed.

For many years, those who wanted to take advantage of fat 512-bit vector registers have been limited to Intel platforms. In fact, AMD lacked support for AVX-512 until the launch of Zen 4 in 2022, and even then it only supported it by double pumping a 256-bit data path. It wasn't until this year's Zen 5 launch the House of Zen added support for a full 512-bit data path.

Going forward, Intel, AMD, and their industry partners aim to avoid this kind of inconsistency by converging around a more uniform implementation. To support this goal, the duo has solicited the help of Broadcom, Dell, Google, HPE, HP, Lenovo, Meta, Microsoft, Oracle, Red Hat, as well as individuals, including Linux kernel-dev Linus Torvalds and Epic's Tim Sweeney.

This advisory group will be tasked with reshaping the x86 ISA to improve cross-compatibility, simplify software development, and address changing demands around emerging technologies.

"We'll have, not only will we have the benefits of performance, flexibility and compatibility across hardware, we'll have it across software, operating systems and a variety of services," Intel EVP of datacenter and AI group Justin Hotard told us.

"I think this will actually enable greater choice in the fundamental products, but reduce the friction of being able to choose from those choices," echoed Norrod.

However, it'll be some time before we see the group's influence realized in products. Norrod emphasized that silicon development can take months if not years. As such it's "not something that's going to reflect into products, I don't believe, in the next year or so."

For end users, the benefits are numerous as in theory taking advantage of either Intel or AMD's products will require less specialization, something we're sure the hyperscalers will appreciate.

For the long-time rivals, however, the change could have major implications for the future development of the architecture. While the two chipmakers have caught up with each other on vector extensions, Intel still has its advanced matrix extensions (AMX) for CPU-based AI inference acceleration.

It remains to be seen whether these extensions will be phased out or if some version of them will eventually make their way into AMD's Epyc and Ryzen processors. We have no doubt that either team's SoC designers would relish the opportunity to reclaim all that die area currently consumed by the NPU.

"I don't think we want to commit to 'we're going to support this or not support this' in a time frame. But I think the intent is we want to support things consistently," Hotard said.

While Norrod and Hotard declined to comment on specific changes coming to x86, recent developments, particularly on Intel's side, give us some idea of the ISA's trajectory.

In June, Intel published an update to its proposed x86S spec, a stripped down version of the ISA free of legacy bloat — most notably 32-bit and 16-bit execution modes. As we understand it, 32-bit code would still be able to run, albeit in a compatibility mode.

There's also the AVX10 spec that we looked at last year, which made many of AVX512's more attractive functions. Under the new spec, AVX10 compatible chips will, for the most part, share a common feature set — including 32 registers, k-masks, and FP16 support — and minimally support 256 bit wide registers.

AVX10 is important for Intel which has transitioned to a dual-stack Xeon roadmap with P-and E-core CPUs, like Granite Rapids and Sierra Forest, the latter of which lacks support for AVX512.

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AMD's dense Zen C-cores don't suffer from this limitation, but can be switched to a double pumped 256-bit data path to achieve lower power AVX512 support. Whether Intel will push ahead with AVX10 or borrow AMD's implementation under the newly formed advisory group is another unknown, but given enough time, we can expect the two chipmakers to coalesce around a common implementation whether it be AVX, AMX or something else.

That's assuming, of course, that Intel and AMD can agree on how to address industry needs.

With that said, a more consistent ISA could help stave off the growing number of Arm-compatible CPUs finding homes in cloud datacenters. While the exact cores used by these chips may differ — most use Arm's Neoverse cores, but some, like Ampere have developed their own — most are using either the older ARMv8 or ARMv9 ISAs, ensuring that with few exceptions code developed on one should run without issue on the other. ®