AMD Says Its FPGA Is Ready To Emulate Your Biggest Chips

The flexibility of field programmable gate arrays (FPGAs) makes them ideal for all kinds of applications ranging from smartNICs, telecom networks, and even for emulating retro game consoles.

However, AMD's – formerly Xilinx's – latest Versal FPGAs unveiled Tuesday can do a bit better than simulate a 30-year-old microprocessor. The parts are designed to emulate, test, and debug chips before they've even been built.

Taping a chip out for manufacturing is an incredibly expensive prospect, and even more so if you discover a defect after the fact. Using these FPGAs, chip designers can "create a digital twin or a digital version of their upcoming ASIC or SOC well ahead of silicon tape out," Rob Bauer, senior product line manager for AMD's Versal family, told The Register. "They can verify, they can begin software development much earlier in the design cycle, etc."

According to Bauer, this is only going to get more difficult for chipmakers as the transition to advanced packaging techniques like 2.5D and 3D chiplet architectures. "If you're a chip designer, no longer are you doing verification and software development for a single die, you're doing it for a multi-die chiplet-based device," he explained.

This is where AMD is positioning its Versal Premium VP1902. Measuring roughly 77x77mm, the massive chip boasts 18.5 million logic cells – twice that of the outgoing VU19P – as well as dedicated Arm cores for control-plane operations, and onboard networking to assist with debugging.

The idea here is that by including general compute and networking functionality, less of the FPGA's logic is used up by I/O, debugging or control plane, and more of it for emulating the ASIC or SoC.

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In addition to doubling the gate density, AMD says the part also offers twice the bandwidth, which translates into a higher effective cloud rate when emulating silicon. Meanwhile, the chip features a new chiplet architecture that places four FPGA tiles in quadrants, which Bauer says helps to reduce latency and congestion as data moves through the chips.

While all of this might sound impressive, anyone who has spent any time playing with emulation will know it tends to be highly inefficient, slow, and expensive compared to running on native hardware, and the situation is no different here.

Emulating modern SoCs with billions of transistors is a pretty resource intensive process to begin with. Depending on the size and complexity of the chip, Bauer says dozens or even hundreds of FPGAs spanning multiple racks may be required, and even then clock speeds are severely limited compared to what you'd find in hard silicon.

According to AMD, while just 24 devices are required to emulate a billion logic gates, it can be scaled out to support up to 60 billion gates at clock speeds in excess of 50MHz.

Bauer notes that the effective clock rate does depend on the number of FPGAs involved. "For example, if you had a piece of IP that can live in a single VP1902, you're gonna see much higher performance," he said.

While AMD's latest FPGA is largely aimed at chipmakers, the company says the chips are also well suited to companies doing firmware development and testing, IP block and subsystem prototyping, peripheral validation, and other test use cases.

As for compatibility, we're told the new chip will take advantage of the same underlying Vivado ML software development suite as the company's previous FPGAs. AMD says it's also working in collaboration with leading EDA vendors, like Cadence, Siemens and Synopsys, to add support for the chip's more advanced features.

AMD's VP1902 is slated to start sampling to customers in Q3 with general availability beginning in early 2024. ®