Rediscovering RISC-V: Apple M1 Sparks Renewed Interest In Non-x86 Architectures

RISC-V is, like x86 and ARM, an instruction set architecture (ISA). Unlike x86 and ARM, it is a free and open standard that anyone can use without getting locked into someone else's processor designs or paying costly license fees.

RISC-V (pronounced RISC-5) is the brainchild of UC Berkeley professors David Patterson and Krste Asanović. Patterson has a talent for catchy acronyms and architectures as a developer of RISC (Reduced Instruction Set Computing) and RAID (Redundant Array of Inexpensive Disks) in the 1980s. They outlined the case for RISC-V in this paper.

What is an ISA?

An ISA as an interface -- similar to an Application Programming Interface (API) -- for CPU operations. A compiler or interpreter translates your high-level language, such as C, into ISA commands for the processor to perform work.

Each ISA instruction is implemented by the underlying hardware. So, ISA designs need to consider how their instructions will affect the price/performance of the CPU. That's why ARM, for example, requires most license holders to use their hardware designs as well.

Reaching the end of Moore's Law, we can't just cram more transistors on a chip. Instead, as Apple's A and M series processors show, adding specialized co-processors -- for codecs, encryption, AI -- to fast general-purpose RISC CPUs can offer stunning application performance and power efficiency.

But a proprietary ISA, like ARM, is expensive. Worse, they typically only allow you to use that ISA's hardware designs, unless, of course, you're one of the large companies -- like Apple -- that can afford a top-tier license and a design team to exploit it. A canned design means architects can't specify tweaks that cut costs and improve performance.

An open and free ISA, like RISC-V, eliminates a lot of this cost, giving small companies the ability to optimize their hardware for their applications. As we move intelligence into ever more cost-sensitive applications, using processors that cost a dollar or less, the need for application and cost-optimized processors is greater than ever.

Why a NEW ISA?

Arguably the first ISA was Alan Turing's machine described in a paper in 1936. With only six instructions, a Turing machine can emulate any computer, although creating smaller instruction sets is a competitive sport, leading to one-instruction designs. 

In the decades since architects have gone down thousands of dead ends, such as decimal -- instead of binary -- encoding, Very Long Instruction Word (VLIW) architectures, and Complex Instruction Set Computing (CISC). We know more today than in the 1970s, so a new ISA can be designed to preserve software investments and designer experience for decades.

RISC-V includes several features designed to ensure a long useful life. These include:

• Base plus extensions. RISC-V offers a small core set of instructions but standard optional extensions for common operations as well as space for entirely new opcodes.
  
  
• Compact instruction encoding. IoT devices must be frugal with memory and storage to meet cost constraints.
  
  
• Quadruple-precision (QP) floating point. Data sets have grown so large in some applications that standard single-precision and double-precision floating point doesn't hack it.
  
  
• 128 bit addressing, in addition to 32 and 64 bit. If they haven't already, warehouse-scale computers will soon bump up against the limits of 64 bit addressing.
  
  

The take

While open operating systems, like Linux, get a lot of attention, ISAs are an even longer-lived foundational technology. The x86 ISA dates back 50 years and today exists as a layer that gets translated to a simpler -- and faster -- underlying hardware architecture. (I suspect this fact is key to the success of the macOS Rosetta 2 translation from x86 code to Apple's M1 code.)

Of course, an open ISA is only part of the solution. Free standard hardware designs -- with tools to design more -- and smart compilers to generate optimized code are vital. That larger project is what Berkeley's Adept Lab is working on.

As computing continues to permeate civilization, the cost of sub-optimal infrastructure will continue to rise. Optimizing for efficiency, long-life, and broad application is vital for humanity's progress in a cyber-enabled world.

Comments welcome.